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FPGA-based implementation of floating point processing element for the design of efficient FIR filters.

Tintu Mary JohnShanty Chacko
Published in: IET Comput. Digit. Tech. (2021)
Keyphrases
  • floating point
  • fir filters
  • hardware architecture
  • data processing
  • fixed point
  • efficient implementation
  • sparse matrices
  • instruction set
  • computationally efficient
  • pairwise
  • memory management
  • finite impulse response