A dynamically reconfigurable interconnect for array processors.
Lizy Kurian JohnE. JohnPublished in: IEEE Trans. Very Large Scale Integr. Syst. (1998)
Keyphrases
- parallel algorithm
- processor array
- parallel processing
- high speed
- parallel computing
- antenna array
- parallel execution
- multiprocessor systems
- shared memory
- high end
- parallel processors
- focal plane
- interconnection networks
- list scheduling
- linear array
- message passing interface
- processing elements
- parallel architecture
- high performance computing