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A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC.
Janet Brunsilius
Eric Siragusa
Steve Kosic
Frank Murden
Ege Yetis
Binh Luu
Jeff Bray
Phil Brown
Allen Barlow
Published in:
ISSCC (2011)
Keyphrases
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power consumption
power supply
hd video
signal to noise ratio
analog to digital converter
low power
high definition
noise reduction
database
single chip
pipeline architecture
low cost
real time
pac man
processing pipeline
image sensor
sampling rate
high speed
circuit design
power dissipation
parallel processing