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Research on reliable on-chip network using asynchronous logic.
Jianlan Guo
Yijun Liu
Yuqiang Chen
Published in:
CIS (2012)
Keyphrases
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delay insensitive
chip design
high speed
real time
network structure
complex networks
network traffic
communication networks
asynchronous circuits
anomaly detection
network architecture
network management
classical logic
high bandwidth
analog vlsi