Low-Power Modified Shift-Add Multiplier Design Using Parallel Prefix Adder.
Rohan PintoKumara ShamaPublished in: J. Circuits Syst. Comput. (2019)
Keyphrases
- low power
- logic circuits
- single chip
- power dissipation
- power consumption
- low power consumption
- high speed
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- cmos technology
- vlsi architecture
- digital signal processing
- gate array
- parallel processing
- ultra low power
- vlsi circuits
- embedded systems
- efficient implementation
- signal processing
- video sequences
- wireless transmission
- signal processor
- nm technology