AN ultra low power fault tolerant SRAM design in 90nm CMOS.
Kuande WangLi ChenJinsheng YangPublished in: CCECE (2009)
Keyphrases
- fault tolerant
- ultra low power
- low power
- fault tolerance
- cmos technology
- power consumption
- single chip
- distributed systems
- nm technology
- circuit design
- low cost
- high speed
- design considerations
- real time
- parallel processing
- digital signal processing
- safety critical
- power reduction
- high assurance
- multistage
- database management systems