Throughput-Optimal Hardware Implementation of LZW Decompression on the FPGA.
Hiroshi KagawaYasuaki ItoKoji NakanoPublished in: CANDAR Workshops (2019)
Keyphrases
- hardware implementation
- field programmable gate array
- compression algorithm
- signal processing
- efficient implementation
- fpga implementation
- hardware architecture
- software implementation
- dedicated hardware
- hardware design
- compression ratio
- image compression
- parallel architecture
- fpga technology
- fpga device
- image processing algorithms
- processing elements
- memory management
- data compression
- pipeline architecture
- pipelined architecture
- compression scheme
- low cost
- image binarization
- shift register
- general purpose
- data structure