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An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis.
Sheng Chou
Cheng-Shen Han
Po-Kai Huang
Ko-Fan Tien
Tsung-Yi Ho
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2011)
Keyphrases
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complex networks
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