A low power monolithic subsampled phase-locked loop architecture for wireless transceivers.
Amr N. HafezMohamed I. ElmasryPublished in: ISCAS (2) (1999)
Keyphrases
- low power
- vlsi architecture
- wireless transmission
- power consumption
- low cost
- high speed
- ultra low power
- mixed signal
- cmos technology
- single chip
- real time
- high power
- phase locked loop
- vlsi circuits
- nm technology
- signal processor
- logic circuits
- image sensor
- gate array
- wireless networks
- digital signal processing
- low power consumption
- wireless communication
- power dissipation
- multiscale