An Implementation of an Instruction Controlled Cache Replacement Policy on a RISC-V Processor.
Riku TakayamaJubee TadaPublished in: CANDARW (2023)
Keyphrases
- instruction set
- replacement policy
- memory subsystem
- floating point
- prefetching
- web caching
- hit rate
- memory access
- computer architecture
- application specific
- buffer management
- proxy cache
- cache misses
- embedded systems
- poisson process
- hit ratio
- level parallelism
- memory hierarchy
- response time
- shared memory multiprocessor
- shared memory multiprocessors
- computation intensive
- memory management
- highly scalable
- hardware implementation
- data access