Design and characterisation of 16×1 parallel outputs SPAD array in 0.18 um CMOS technology.

Suhaila Isaak Mark C. Pitter Steve Bull Ian Harrison

Published in: APCCAS (2010)

Keyphrases

cmos technology
parallel processing
low power
power consumption
power dissipation
low voltage
design process
spl times
user interface
image sensor
image processing
design methodology
single chip