A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS.

Zhiliang Qiao Xiong Zhou Qiang Li

Published in: MWSCAS (2013)

Keyphrases

high speed
delta sigma
power consumption
analog to digital converter
low power
analog vlsi
low cost
circuit design
power supply
low voltage
delay insensitive
sigma delta
parallel processing
cmos image sensor
high signal to noise ratio
image sensor
vlsi circuits
hd video
subtractive clustering
image quality
real time