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A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.
Xinyu Xu
Woogeun Rhee
Zhihua Wang
Published in:
ISCAS (2020)
Keyphrases
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low voltage
power line
design considerations
power management
power consumption
pattern recognition
cmos technology
high speed
parallel processing