A novel gate grading approach for soft error tolerance in combinational circuits.

Mohammad Saeed Ansari Ali Mahani Jie Han Bruce F. Cockburn

Published in: CCECE (2016)

Keyphrases

error tolerance
logic circuits
cmos technology
asynchronous circuits
low power
high speed
power consumption
digital curves
power dissipation
field effect transistors
wavelet transform
sample size
low voltage