A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-µm CMOS.

Jarkko Jussila Pete Sivonen

Published in: IEEE J. Solid State Circuits (2008)

Keyphrases

noise reduction
noise level
high speed
noise sensitivity
noise free
signal to noise ratio
random noise
power consumption
closed form
noisy data
noise model
image noise
cmos image sensor
neural network
analog vlsi
noisy environments
additive noise
low power