Low-Power Counter-Based Delay Line Design For DPWM.
Cheng-Jie YangMing-Jie LiChen-Yueh LiuMing-Hwa SheuChi-Chia SunPublished in: ICCE-TW (2019)
Keyphrases
- low power
- single chip
- low cost
- low power consumption
- high speed
- power consumption
- vlsi architecture
- logic circuits
- gate array
- cmos technology
- mixed signal
- power dissipation
- real time
- digital signal processing
- wireless transmission
- vlsi circuits
- high power
- ultra low power
- design methodology
- efficient implementation
- design process
- image processing