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A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification.

Weirong JiangViktor K. Prasanna
Published in: ASAP (2009)
Keyphrases
  • high speed
  • parallel architecture
  • hardware implementation
  • pattern recognition
  • neural network
  • real time
  • machine learning
  • feature extraction
  • dynamic programming
  • parallel implementation
  • systolic array