Login / Signup

Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology.

C. A. LuH. P. LeeH. C. ChenY. C. LinY. H. ChungS. H. WangJ. Y. YehV. S. ChangM. C. ChiangW. ChangH. C. ChungC. F. ChengH. H. HsuH. H. LiuWilliam P. N. ChenC. Y. Lin
Published in: VLSI Technology and Circuits (2023)
Keyphrases
  • cmos technology
  • low power
  • spl times
  • power consumption
  • low voltage
  • parallel processing
  • mixed signal
  • low cost
  • high speed
  • power dissipation
  • efficient implementation
  • image sensor