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Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology.

C. A. LuH. P. LeeH. C. ChenY. C. LinY. H. ChungS. H. WangJ. Y. YehV. S. ChangM. C. ChiangW. ChangH. C. ChungC. F. ChengH. H. HsuH. H. LiuWilliam P. N. ChenC. Y. Lin
Published in: VLSI Technology and Circuits (2023)
Keyphrases
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