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A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS.
Xuan-Thuan Nguyen
Trong-Thuc Hoang
Hong-Thu Nguyen
Katsumi Inoue
Cong-Kha Pham
Published in:
Microprocess. Microsystems (2020)
Keyphrases
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power consumption
nm technology
power dissipation
power reduction
cmos technology
low power
clock gating
high speed
power management
power saving
silicon on insulator
flip flops
low cost
low voltage
random access memory