Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures.
Travis BoratenAvinash Karanth KodiPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2018)
Keyphrases
- network on chip
- interconnection networks
- routing algorithm
- multi processor
- network simulator
- packet switched
- fault tolerant
- data transfer
- multi core processors
- multistage
- shortest path
- parallel algorithm
- program execution
- power dissipation
- end to end
- message passing
- real time
- multipath
- single processor
- mobile ad hoc networks
- ad hoc networks
- network traffic
- anomaly detection
- wireless sensor networks