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Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topology.
Xianfang Tan
Lei Zhang
Shankar Neelkrishnan
Mei Yang
Yingtao Jiang
Yulu Yang
Published in:
ACM Great Lakes Symposium on VLSI (2008)
Keyphrases
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fault tolerant
interconnection networks
fault tolerance
network on chip
distributed systems
load balancing
web services
multistage
design methodology
fault isolation
packet switched