System Level Formal Verification via Model Checking Driven Simulation.
Toni ManciniFederico MariAnnalisa MassiniIgor MelattiFabio MerliEnrico TronciPublished in: CAV (2013)
Keyphrases
- formal verification
- model checking
- model checker
- temporal logic
- automated verification
- symbolic model checking
- bounded model checking
- finite state
- formal specification
- temporal properties
- reachability analysis
- timed automata
- verification method
- computation tree logic
- process algebra
- pspace complete
- transition systems
- epistemic logic
- concurrent systems
- description language
- asynchronous circuits
- reactive systems
- artificial intelligence
- specification language
- knowledge representation