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A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic.
Sonal Yadav
Vijay Laxmi
Manoj Singh Gaur
Published in:
VLSI Design (2016)
Keyphrases
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routing algorithm
network on chip
network traffic
real time
link failure
multi processor
shortest path
power consumption
wireless sensor networks
logic programming
ad hoc networks
traffic flow
traffic engineering
interconnection networks