Low Power Design of Asynchronous Datapath for LDPC Decoder.
Xiaobo JiangDesheng YeHongyuan LiWentao WuXiangmin XuPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2013)
Keyphrases
- low power
- vlsi architecture
- single chip
- low density parity check
- low cost
- low power consumption
- power consumption
- logic circuits
- high speed
- digital signal processing
- delay insensitive
- mixed signal
- gate array
- real time
- cmos technology
- ldpc codes
- power dissipation
- circuit design
- video codec
- low complexity
- ultra low power
- multi channel
- vlsi circuits
- video coding