Simplified partially parallel DVB-S2 LDPC decoder architectural design based on FPGA.
Wenjing WangLixin LiHuisheng ZhangPublished in: ICCC (2014)
Keyphrases
- architectural design
- ldpc codes
- low density parity check
- fpga implementation
- design decisions
- parallel hardware
- distributed source coding
- software architecture
- distributed video coding
- turbo codes
- decoding algorithm
- detailed design
- error correction
- compressive sensing
- low complexity
- field programmable gate array
- video transmission
- channel coding
- rate allocation
- wireless channels
- image transmission
- computational complexity
- video codec
- parallel computing
- error concealment
- hardware implementation
- trade off