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Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme
S. Saravanan
M. Madheswaran
Published in:
CoRR (2010)
Keyphrases
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low power
encoding scheme
low cost
high speed
low power consumption
single chip
vlsi architecture
power consumption
logic circuits
gate array
power dissipation
digital signal processing
data analysis
genetic algorithm
cmos technology
database systems
nm technology