A Novel Speedup Evaluation for Multicore Architecture Based Topology of On-Chip Memory.
Xiaojun WangFeng ShiHong ZhangPublished in: PAAP (2019)
Keyphrases
- level parallelism
- memory management
- memory access
- multithreading
- memory bandwidth
- analog vlsi
- real time
- computing power
- management system
- instruction set
- vlsi implementation
- memory hierarchy
- orders of magnitude
- low cost
- host computer
- memory subsystem
- digital signal processors
- computational power
- random access
- circuit design
- data flow
- hardware implementation
- associative memory
- parallel processing