Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.

Stefan Rusu Harry Muljono Brian S. Cherkauer

Published in: IEEE Micro (2004)

Keyphrases

embedded processors
processor core
cache misses
prefetching
memory access
memory subsystem
query processing
memory hierarchy
multithreading
database workloads
database systems
high speed
low frequency
single chip
memory management
shared memory multiprocessors