Stretching the capacity of hardware transactional memory in IBM POWER architectures.
Ricardo FilipeShady IssaPaolo RomanoJoão BarretoPublished in: PPoPP (2019)
Keyphrases
- parallel architectures
- transactional memory
- speculative execution
- blue gene
- massively parallel
- computing systems
- commodity hardware
- field programmable gate array
- hardware design
- parallel processing
- highly parallel
- parallel computing
- hardware and software
- low cost
- address space
- parallel execution
- shared memory
- hardware implementation
- high end
- parallel computers
- parallel programming
- efficient implementation
- real time
- concurrency control
- open source
- response time
- general purpose
- high level
- image processing