Extremely Large Breakdown to Snapback Voltage Offset $(\mathrm{V}_{\mathrm{t}1} > > \mathrm{V}_{\text{BD}})$: Another Way to Improve ESD Resilience of LDMOS Devices.
Aakanksha MishraBoeila Sampath KumarM. MonishmuraliShaik Ahamed SuzaadShubham KumarKiran Pote SanjayAmit Kumar SinghAnkur GuptaMayank ShrivastavaPublished in: IRPS (2023)