Login / Signup

An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS.

Van Nhan NguyenXuan Thanh PhamJong-Wook Lee
Published in: IEEE Trans. Instrum. Meas. (2022)
Keyphrases
  • feature points
  • low cost
  • dynamic environments
  • real time
  • low resolution
  • matching algorithm
  • power consumption
  • nm technology
  • high speed
  • graph matching
  • cmos technology
  • delay insensitive
  • vlsi circuits