Improving Model Checking Stateful Timed CSP with non-Zenoness through Clock-Symmetry Reduction.
Yuanjie SiJun SunYang LiuTing WangPublished in: ICFEM (2013)
Keyphrases
- model checking
- timed automata
- partial order reduction
- finite state machines
- temporal logic
- formal verification
- verification method
- temporal properties
- automated verification
- reachability analysis
- model checker
- formal specification
- finite state
- constraint satisfaction problems
- petri net
- formal methods
- computation tree logic
- concurrent systems
- symbolic model checking
- pspace complete
- bounded model checking
- process algebra
- constraint satisfaction
- asynchronous circuits
- orders of magnitude
- artificial intelligence
- binary decision diagrams
- first order logic
- linear temporal logic
- theorem proving
- epistemic logic
- alternating time temporal logic