On-chip I-V variability and random telegraph noise characterization in 28 nm CMOS.
Amy WhitcombeScott TaylorMartin DenhamVladimir M. MilovanovicBorivoje NikolicPublished in: ESSDERC (2016)
Keyphrases
- cmos technology
- nm technology
- silicon on insulator
- analog vlsi
- high speed
- low cost
- metal oxide semiconductor
- low power
- circuit design
- power consumption
- cmos image sensor
- image sensor
- single chip
- low voltage
- chip design
- parallel processing
- random access memory
- noise model
- real time
- power dissipation
- signal to noise ratio
- noisy data
- image noise
- mixed signal
- noise level
- random noise
- low power consumption
- software product line
- median filter
- ibm power processor
- integrated circuit
- noise reduction
- missing data
- ultra low power