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Estimation of high performance in Schmitt triggers with stacking power-gating techniques in 45 nm CMOS technology.
Anshul Saxena
Akansha Shrivastava
Shyam Akashe
Published in:
Int. J. Commun. Syst. (2014)
Keyphrases
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cmos technology
power consumption
low power
power dissipation
silicon on insulator
embedded dram
spl times
low voltage
power management
ibm power processor
parallel processing
low cost
signal processing
image sensor
clock frequency
digital signal processing
image processing
high speed
image analysis