An on-chip cache compression technique to reduce decompression overhead and design complexity.

Jang-Soo Lee Won-Kee Hong Shin-Dug Kim

Published in: J. Syst. Archit. (2000)

Keyphrases

data compression
compression ratio
compression scheme
image compression
compression algorithm
single chip
high speed
physical design
programmable logic
memory hierarchy
data structure
circuit design
compressed data
memory access