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A Novel Concept for High-Speed Time Switch Approaching Memory Read Cycle Limit.
Yousuke Yamamoto
Hiroshi Miyanaga
Yoshiji Kobayashi
Yasukazu Terada
Naoaki Yamanaka
Published in:
IEEE Trans. Commun. (1986)
Keyphrases
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high speed
low power
real time
frame rate
neural network
information retrieval
memory requirements
high speed networks
decision trees
case study
data structure
artificial neural networks
memory usage
random access