A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS.

Xiaolu Liu Na Yan Xi Tan Hao Min

Published in: ASICON (2011)

Keyphrases

user friendly
high speed
phase locked loop
analog vlsi
low cost
high resolution
neural network
consequence finding
power consumption
low resolution
vlsi circuits
real time
minimum cost
power law
image sensor
circuit design
low voltage
delay insensitive
sensor networks