Low-Power Optimization Design of CMOS Phase-Locked Loop for WiFi-6E Applications.
Yue-Fang KuoShuo HanPublished in: ICCE-TW (2022)
Keyphrases
- low power
- power consumption
- single chip
- high speed
- low cost
- cmos technology
- low power consumption
- vlsi architecture
- power dissipation
- wireless transmission
- mixed signal
- logic circuits
- digital signal processing
- ultra low power
- nm technology
- phase locked loop
- wifi
- gate array
- cmos image sensor
- power reduction
- image sensor
- vlsi circuits
- circuit design
- delay insensitive
- real time
- wireless communication