Design of Low-Power Memory-Efficient Viterbi Decoder.
Lupin ChenJinjin HeZhongfeng WangPublished in: SiPS (2007)
Keyphrases
- low power
- memory efficient
- single chip
- power consumption
- low power consumption
- high speed
- vlsi architecture
- low cost
- cmos technology
- logic circuits
- digital signal processing
- mixed signal
- gate array
- power dissipation
- power reduction
- vlsi circuits
- high power
- nm technology
- design methodology
- low complexity
- design process
- motion estimation