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A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies.
Maryam Bahmani
Abbas Sheibanyrad
Frédéric Pétrot
Florentine Dubois
Paolo Durante
Published in:
ISVLSI (2012)
Keyphrases
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local area network
network on chip
real time
genetic algorithm
data sets
response time
high speed
power consumption
efficient implementation
implementation details