Investigating cache energy and latency break-even points in high performance processors.
Kaveh Jokar DerisAmirali BaniasadiPublished in: SIGARCH Comput. Archit. News (2007)
Keyphrases
- embedded processors
- prefetching
- single chip
- parallel implementation
- low latency
- response time
- energy consumption
- signal processor
- point sets
- hit ratio
- highly parallel
- distributed memory
- memory subsystem
- low overhead
- parallel algorithm
- data points
- replacement policy
- multithreading
- web caching
- energy minimization
- feature points
- data structure
- access patterns
- energy efficient
- energy efficiency
- access latency