A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA.
Tengjie SuiZhixiang ZhaoSiwei XieYangze XieYanyan ZhaoQiu HuangJianfeng XuQiyu PengPublished in: IEEE Trans. Instrum. Meas. (2019)
Keyphrases
- low cost
- reconfigurable hardware
- low power consumption
- low power
- hardware and software
- data conversion
- data acquisition
- single chip
- analog to digital converter
- digital camera
- hardware implementation
- real time
- digital media
- high speed
- high resolution
- neural network
- field programmable gate array
- software implementation
- control system
- root mean square
- camera phones
- pipelined architecture