Employing Multiple CUDA Devices to Accelerate LTL Model Checking.
Jiri BarnatPetr BauchLubos BrimMilan CeskaPublished in: ICPADS (2010)
Keyphrases
- model checking
- temporal logic
- formal verification
- bounded model checking
- automated verification
- partial order reduction
- temporal properties
- finite state
- linear temporal logic
- formal specification
- symbolic model checking
- verification method
- concurrent systems
- transition systems
- reachability analysis
- model checker
- pspace complete
- computation tree logic
- finite state machines
- epistemic logic
- asynchronous circuits
- timed automata
- process algebra
- linear time temporal logic
- formal methods
- software engineering