Fault tolerant bus architecture for deep submicron based processors.
N. VenkateswaranS. BalajiV. SridharPublished in: SIGARCH Comput. Archit. News (2005)
Keyphrases
- fault tolerant
- fault tolerance
- distributed systems
- state machine
- parallel algorithm
- high availability
- instruction set
- management system
- interconnection networks
- parallel architecture
- parallel processing
- processing elements
- load balancing
- random access
- high assurance
- hardware architecture
- parallel computers
- low power
- high speed