Securing netlist-level FPGA design through exploiting process variation and degradation.
Jason Xin ZhengMiodrag PotkonjakPublished in: FPGA (2012)
Keyphrases
- design process
- high speed
- single chip
- design decisions
- real time image processing
- building blocks
- software architecture
- levels of abstraction
- conceptual model
- fpga implementation
- design processes
- hardware architecture
- hardware design
- product development
- hardware implementation
- real time
- process model
- knowledge based systems
- image processing
- knowledge base
- data sets