High-speed Instruction-set Coprocessor for Lattice-based Key Encapsulation Mechanism: Saber in Hardware.
Sujoy Sinha RoyAndrea BassoPublished in: IACR Trans. Cryptogr. Hardw. Embed. Syst. (2020)
Keyphrases
- instruction set
- high speed
- floating point
- computer architecture
- application specific
- dedicated hardware
- embedded systems
- real time
- ibm power processor
- memory subsystem
- floating point arithmetic
- instruction set architecture
- memory access
- data processing
- massively parallel
- hardware implementation
- virtual machine
- fixed point
- level parallelism
- signal processing
- source code
- low cost
- object oriented