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A scalable multi-core architecture with heterogeneous memory structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).
Saber Moradi
Qiao Ning
Fabio Stefanini
Giacomo Indiveri
Published in:
CoRR (2017)
Keyphrases
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multi core architecture
parallel processing
parallel algorithm
multi core processors
single instruction multiple data
memory requirements
processing elements
commodity hardware