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Analyzing the Single Event Upset Sensitivity of Digital Clock Manager in Virtex-5 FPGA.
Tingting Yu
Lei Chen
Xuewu Li
Shuo Wang
Jing Zhou
Published in:
IEEA (2017)
Keyphrases
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fpga device
hardware implementation
high speed
field programmable gate array
real time
low cost
real time image processing
reconfigurable hardware
signal processing
database systems
pattern recognition
event detection