Bitstream relocation with local clock domains for partially reconfigurable FPGAs.
Adam FlynnAnn Gordon-RossAlan D. GeorgePublished in: DATE (2009)
Keyphrases
- bitstream
- coding scheme
- bit rate
- field programmable gate array
- hardware implementation
- video quality
- compression algorithm
- scalable video coding
- low cost
- error resilience
- quality degradation
- video transmission
- coded video
- error resilient
- error concealment
- compressed domain
- reconfigurable hardware
- smart camera
- scalable video
- rate allocation
- wavelet coefficients
- high speed
- bit plane
- compressed video
- frame rate
- video coding
- fine grain
- probability model
- rate distortion
- transform domain
- rate distortion optimized
- video streaming
- high quality