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A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.
Shan Jiang
Manh Anh Do
Kiat Seng Yeo
Published in:
VLSI-SoC (2006)
Keyphrases
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mixed mode
high speed
cmos technology
low power
circuit design
nm technology
analog vlsi
low voltage
power consumption
power dissipation
delay insensitive
parallel processing
vlsi circuits
flip flops
low cost
image sensor
data processing
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